The present invention relates to electrically writable non-volatile semiconductor devices (EEPROMs), and more particularly to an EEPROM employing a NAND type cell array.
In the past, NAND-type flash EEPROMs are known as highly integratable EEPROMs. Memory transistors arranged in rows columns and composing a NAND-type flash EEPROM each have a stacked gate structure of a charge storage layer (a floating gate), formed on a semiconductor substrate through an insulting film, and a control gate. The memory transistors in each row or column are connected in series such that any adjacent transistors share a source and drain diffusion layer. Each string of such series-connected transistors has a pair of select gate transistors one provided at each end thereof. Thus, a NAND cell (unit) is formed.
Each of the transistors stores data in a non-volatile manner in a charge storage state of the floating gate thereof. More specifically, it stores binary data, that is, data “0” involving a high threshold voltage representing that electrons have been injected into the floating gate from a channel thereof, and data “1” involving a low threshold voltage representing that electrons have been discharged from the floating gate to the channel. Recently, a multivalued storage system, for example, involving four numerical values including subdividing threshold distribution control is employed.
In data writing, data stored in all the memory transistors of the NAND cell block is beforehand erased collectively. This is performed by applying a voltage Vss to all the control gate lines (word lines) of a selected NAND cell block, and a positive boosted voltage (erasing voltage) to a p-type well of the cell array to cause electrons in the respective floating gates of the memory transistors to discharge into their channels. Thus, data in all the memory transistors of the NAND cell block is set to “1” (erased state).
After erasing all the data collectively in the respective NAND cells, data writing is sequentially performed collectively into the memory transistors of the NAND cell arranged along the respective selected control gate lines, starting with the memory transistors arranged along the control gate line nearest the source line usually, referred to as a page. When a positive boosted voltage Vpgm is applied to a selected word line, electrons are then injected into a floating gate of the selected memory transistor from a channel in the NAND cell (so-called “0 write”) in the case of “0” data writing. In the case of “1” data writing, electron injection is inhibited (so-called “write inhibit” or “1” write).
Data writing into the respective memory transistors of each NAND cell is performed by controlling the channel potential of a selected memory transistor depending upon write data “0” or “1”. For example, in the case of data “0” writing, the channel potential is kept low. Thus, when the write voltage is applied to the control gate of the selected memory transistor, its floating gate is boosted to thereby cause electron injection into the floating gate. In the case of “1” data writing (or write inhibit), the channel potential is boosted to thereby inhibit electron injection into the floating gate.
There are various systems for controlling channel potentials in the case of data writing. A self-boost system is known in the past, in which when “1” data is to be written, the channel of a selected memory transistor is placed in a floating state and the channel potential is boosted by capacitive coupling of the channel to the control gate. More particularly, before the write voltage is applied to the control gate line, Vss or Vdd is applied to a bit line depending upon write data “0” or “1” to turn on a selected gate transistor on the bit line side and to turnoff a selected gate transistor on the source side. Thus, when “0” data is to be written, Vss is transferred to the NAND cell channel. When “1” data is to be written, the NAND cell channel is precharged to a potential equal to the voltage (for example, Vdd+α) applied to the gate of the selected gate transistor minus the threshold voltage of the selected gate transistor to thereby place the NAND cell channel in a floating state.
Then, when the write voltage is applied to the selected gate line, a high field is applied across a gate insulating film underlying the floating gate and electrons are, for example, tunnel injected into the floating gate because the channel of the selected memory transistor is clamped to the low voltage Vss in the case of “0” data writing. In the case of “1” data writing, the channel of a selected memory transistor in the floating state is boosted through capacitive coupling to the control gate of the selected memory transistor. More specifically, one write voltage (for example, of 20V) applied to the selected control gate line and a plurality of medium voltages (for example, of 10V) applied to a plurality of non-selected control gate lines cause capacitive coupling to boost the channel potential to 6V to thereby produce a voltage difference of 14V between the channel and the selected control gate line. Thus, writing is inhibited.
As another example of the self-boost system, a special system has been proposed in which all the memory transistors of a NAND cell arranged between its selected memory transistor and the bit line are boosted as a unit (Japanese Patent Laid Open No. 10-283788). In this case, Vss is applied to the control gate of a memory transistor adjacent to the source electrode of the selected memory transistor to cut off its channel. A write voltage is then applied to the control gate of the selected memory transistor. A medium voltage is applied to the control gates of the other memory transistors.
This cuts off the channels of the written memory transistors arranged on the source side from the selected memory transistor. When data to be written into the selected memory transistor is “0”, Vss is transferred to the channel of the selected memory transistor and electrons are injected into the floating gate of the selected memory transistor. Since the medium voltage is applied to the control gates of the memory transistors arranged on the bit line from the selected memory transistor, no electron injection occurs in those memory transistors. When the write data is “1”, the channel of the selected memory transistor and the other memory transistors arranged on the bit line from the selected memory transistor can be capacitively coupled together to their control gates to thereby boost the channels to inhibit electron injection.
Recently, the self-boost system used generally is a Local Self-Boost (LSB) system. Referring to FIG. 5, this system will be explained when “1” data is to be written. Two memory transistors provided one on each side of a selected memory transistor are turned off. Thus, only the channel of the selected memory transistor is placed in a floating state where it is cut off from other memory transistors to thereby boost the channel of the selected memory transistor. A medium voltage is applied to the control gates of the memory transistors other than the three memory transistors (including the selected memory transistor and the adjacent memory transistors).
Also, in this case Vss is transferred from a “0”-write bit line to the channel of the selected memory transistor. When the write voltage is applied to the control gate of the selected memory transistor, electrons are injected into the floating gate thereof. In the case of a “1” write bit line, the two memory transistors arranged one adjacent to each side of the selected transistor are respectively turned off and only the channel of the selected memory transistor is placed in a floating state. Only the channel of the selected memory transistor is boosted by capacitive coupling to the control gate so that electron injection is inhibited.
As described above, a multivalued system is also used as a data storing system for an NAND type flash EEPROM. This system has a merit over a binary system that compared to the binary system the former system is capable of recording a double quantity of data in a memory cell array having the same area as the binary system. However, the former system also has a drawback that write control is difficult necessarily because a range of threshold voltages of memory transistors to be used for data recording expands. For example, in the case of “1” writing, the channel potential of the memory transistor concerned is insufficient, so that wrong writing involving wrong injection of electrons into the floating gate of the memory transistor can occur. It is very important to prevent such wrong writing. Especially, the LSB system is greatly expected as being capable of preventing wrong writing when a multivalued storage system is employed.
In the LSB system, when “1” data is to be written, the channel of the selected memory transistor is boosted by tuning off the two memory transistors disposed one adjacent to each side of the selected memory transistor. At this time, if the two adjacent memory transistors can be completely cut off, the boost area is limited to the channel and diffusion layer of the selected memory transistor. Thus, the narrow area only needs to be boosted with a write voltage Vsgm. Therefore, there is a probability that the channel can be boosted efficiently.
With this LSB system, however, when “1” is to be written into a second memory transistor from the bit line or a common source line, situations are different in writing from those with the other memory transistors. Therefore, there is a probability that the channel will be boosted insufficiently which will be described more specifically next with reference to FIGS. 12 and 13.
FIGS. 12 and 13 each shows a relationship among voltages applied to the respective control gates of the memory transistors of the NAND cell, and boosting of the channels of third and second selected memory transistors, respectively, from the bit line side. As shown in FIG. 12, when the third memory transistor is selected by a control gate line CG2, Vss=0 V is applied to control gate lines CG1 and CG3 each adjacent to the control gate line CG2, and a medium voltage Vpass is applied to the respective other control gate lines CG0, CG4, . . . .
If at this time the medium voltage Vpass applied is, for example, 10 V and a capacitive coupling ratio is 50%, the channel underlying the control gate line CG0 is boosted to about 5 V. The channel underlying the control gate line CG0 functions as a source of the second memory transistor to which Vss was applied. The gate-source voltage of the second memory transistor becomes −5 V. If the threshold of this memory transistor in an erased state is higher than −5 V, the memory transistor is turned off. Likewise, the channel of a fourth memory transistor to be controlled by the control gate line CG3 is also turned off.
Thus, the channel, shown hatched, (including the source and drain electrons) of the third memory transistor to which the write voltage Vpgm is applied is placed in a floating state and boosted by the write voltage Vpgm.
In contrast, when a second memory transistor (on control gate line CG1) from the bit line side is selected, situations shown in FIG. 13 appear. Vss is applied to a control gate line CG0 adjacent to the control gate line CG1 on the bit line side. A diffusion layer of the memory transistor functioning as its source on the control gate line CG0 on the select gate transistor side has a potential Vdd−Vth (where Vth is a threshold voltage of the select gate transistor) because Vdd has been applied to the selected gate line SGD. If, for example, Vdd=3 V and Vth=1 V, the gate-source voltage of the memory transistor on the control gate line CG0 is −2 V. If the threshold voltage of the memory transistor in an erased state is lower than −2 V, the first memory transistor to which Vss is applied via the control gate line CG0 is not turned off.
Thus, the channel to be boosted by the write voltage Vpgm applied to the selected control gate line CG1 is shown by a hatched area that unites the channels of the two memory transistors on the control gate lines CG0 and CG1. In other words, the channel having a double area compared to FIG. 12 must be boosted by the write voltage Vpgm. As a result, the boosting efficiency will decrease, which would lead to wrong writing involving electron injection into the floating gate.
Similar situations will also occur when a second memory transistor on the common source side is selected.
A tendency to subdivision has brought about the gate lengths of the memory transistors reaching a gradation of submicrons, which makes it difficult to get a good cutoff characteristic actually. From a standpoint of process, the tendency to subdivision thins the gate of a memory transistor provided at each end of a NAND cell in lithography. This causes uneven lengths of the gates due to processing to deteriorate the cutoff characteristic. Thus, it is expected that the above problems will more and more remarkable from now on.